Background

Copper has been the wiring metal of choice in electronic devices because of its ductility, malleability and excellent conductivity characteristics. Especially in semiconductor fabrication, copper is used as an interconnect material which plays an important role in the power supply and electric signal distribution.

Ultimate processor speed limit and chip performance are determined by the frequency at which transistors can turn on and off. Since clock frequency increases with density of transistors, which requires decreasing transistor size, advances in chip speeds have been achieved by shrinking the feature sizes and increasing the count. Currently, the speed limit and performance of a chip is set by signal propagation delays and the time constant of the copper interconnects, as well as thermal constraints set by material properties and practical limits set by customers who purchase semiconductors to integrate into computing devices.

Copper interconnects of integrated circuits are fabricated by the dual damascene process which involves defining the line pattern using photolithography techniques and filling the patterned channel with copper by an electrochemical method. Finally, the excess copper removed by chemical mechanical planarization (chemical “sanding” of the surface). Copper is known to be a fast diffuser into silicon and its oxide dielectrics. This causes deep level defects which may lead to poor performance or chip failure. By using a titanium‑based channel coating, manufacturers can localize copper to where it is desired, but these methods have resulted in numerous and compounding compromises as chip feature size has reduced to increase performance.

With the ever-decreasing copper wire interconnect dimensions, the resistance of the narrow conductive channel is increasing due to electron scattering by the grain boundaries and at wire surfaces. Increased resistance adversely contributes to the overall signal propagation delay. In the modern chips, total resistance of the copper interconnect structure is a significant factor that affects the chips’ performance. Furthermore, as the area of copper interconnects increase, the capacitance between the closely‑squeezed conductive channels also increases. Both effects significantly increase in the RC signal delay, which results in degraded performance of the chips.

As semiconductor feature sizes are shrinking to few nanometer scales, it is becoming very challenging to have these layers and fill them with copper. Ultimately, the fabrication of interconnects in a dual damascene process is reaching its fundamental limits. Therefore, innovative materials and process solutions are critical to sustaining the miniaturization and performance trends.

Technology Overview

Among all 1‑dimensional nanomaterials, copper has the second highest electrical conductivity among metals, is highly abundant, low cost, and well‑understood by the semiconductor industry. Thus copper nanowires are considered promising as building blocks for many applications, such as flexible & transparent electrodes, conductive inks, catalyst, and interconnects.

Copper has successfully been used as an interconnect material on-chip since 1997; therefore, copper nanowires are the ideal candidates for many micro and functional nanoscale devices, however, until now no one has managed to develop a simple and reliable technique to assemble the copper nanowires into a functional device.

Magnetic field‑assisted assembly techniques involve applying an external magnetic field to directionally organize the magnetically‑active nanowires suspended in solution. In the presence of applied magnetic field, each nanowire will polarize and orient themselves parallel to the applied magnetic field direction (). An added advantage of this technique is the assembled nanowires form chain-like structures by connecting in a head‑to‑tail fashion, which gives a continuous network of even with varying lengths. These kinds of continuous networks are ideal for the best electrical performance ().

Although applications of copper nanowires have been demonstrated in a wide range of devices (e.g.,transparent and flexible electrodes and conductive ink, etc.), oxidation of pure copper into copper oxides limits its reliable performance. Also, very limited success has been achieved in controlling the orientation and positioning of copper nanowires, which is critical for assembly of these into complex functional devices. The above two challenges are addressed by in this technology by coating a thin layer of oxidation resistant and ferromagnetic nickel onto the copper nanowire surface with electrolysis process. The nickel coating protects the copper nanowire core from oxidation while generating a magnetic response needed for bulk alignment. The orientation of the copper/nickel nanowires is controlled by applying a uniform magnetic field to the nanowires in solution deposited onto the silicon wafer surface ().

Systematic studies of alignment phenomenon were undertaken. In the absence of a magnetic field, the nanowires arranged into random directions, whereas, with an applied magnetic field, the majority of the nanowires aligned to the applied magnetic field (see angular distribution in ).

A production‑ready flow process has already been demonstrated for this technology using standard semiconductor techniques, including photolithography and thiol functionalization. The chemical interaction of thiol functional groups to copper and nickel is exploited to strongly adhere the nanowires after deposition onto the silicon substrate which is functionalized prior to copper nanowire application with dangling thiol functional groups ().

Benefits

Increased thermal and electrical stability compared to pure copper nanowires
Protection from oxidation due to nickel barrier layer
Scalable production techniques have been lab‑tested
Superior (lower) thermal resistance compared to coper, indium, and other candidate interconnect species for feature size <20nm
Enables transparent conductive grids on glass and polymer substrates

Opportunity

Partnership for collaborative research and/or licensing of the patents currently in prosecution stage.

Copper Nanowires for Semiconductor Interconnects

IP Status

Seeking