Background

A traditional method of optimizing the test manufacturing flow is to characterize a sufficiently large sample of units of a specific product by measuring the multiple parametric attributes over a range of temperatures, voltages, and frequencies corresponding to possible test and use conditions of a future product.

Test set points and limits are then found by filtering the data and computing figures of merit (FOMs) such as yield loss, overkill, and end-use fail fraction so that manufacturing cost, and quality and reliability targets are met.

What is needed is a way to do this better and earlier in the product lifecycle.

Technology Overview

The method includes acquiring data from a test vehicle, fitting the data to a copula-based statistical model to compute producer- and customer-oriented figures of merit of a product, different from the test vehicle. The statistical model is copula-based and so can take into account dependency among attributes of the product. The copula-based model has features, which enable significant computational efficiencies. The copula-based statistical model also describes the dependency structure of the data.

Benefits

Faster, more precise and thus cheaper tool for test manufacturing process.
Different size, fault tolerance schemes, test coverage, end-use (datasheet), and test condition specifications of the product may be modeled.
Separation of modeling of marginal distributions from modeling the dependency structure of the data is a key aspect and major benefit.
An important benefit of this model is that fitting of marginal distributions is completely decoupled from fitting of the copula, so that the marginal and copula model-fitting steps may be done in any sequence.
Another benefit of copula models is that it provides a deterministic semi-analytical way to compute figures of merit used to characterize, and so specify, the test manufacturing process.

Opportunity

Great opportunity to partner with existing test manufacturing solution provider or manufacturer of electronic systems and integrated circuits.

System for Management of Semiconductor Manufacturing Tests throughout the Product Lifecycle

Patents

IP Status